Recently, a liquid crystal display (LCD), featured by thin thickness, light weight and low power consumption, has become popular as display, and has been in widespread use for a display unit of mobile equipment, such as portable telephone sets (mobile phone or cellular phone), PDA (Personal Digital Assistant) or a notebook personal computer. In these days, with progress in the technique for increasing the size of a viewing area of the liquid crystal display and for coping with moving pictures, the liquid crystal display is now usable not only for mobile application but also for a stationary large viewing area display or for a large viewing area liquid crystal television set. For these sorts of the liquid crystal display, a liquid crystal display of an active matrix driving scheme, capable of high definition representation, has come to be used.
Initially, a typical configuration of a liquid crystal display of the active matrix driving scheme is briefly described with reference to FIG. 15. In FIG. 15, certain principal components, connected to each pixel of a liquid crystal display unit, are schematically shown by equivalent circuits.
In general, a display unit 960 of a liquid crystal display of an active matrix driving scheme includes a semiconductor substrate, an opposite substrate, including a transparent electrode 967 that covers the entire surface of the opposite substrate, and a liquid crystal. The semiconductor substrate includes a matrix array of larger numbers of transparent pixel electrodes 964 and larger numbers of thin-film transistors (TFTs) 963. In the case of a color SXGA panel, for example, 1280×3 pixel columns by 1024 pixel rows make up the matrix array. The liquid crystal is sealed in-between the semiconductor substrate and the opposite substrate that are arranged facing each other. The liquid crystal is capacitive and forms a capacitor 965 in-between the pixel electrode 964 and the electrode 967. There may further be provided an auxiliary capacitor 966 for assisting in the capacitive performance of the liquid crystal.
With the above-described liquid crystal display, the TFT 963, having the switching function, is controlled to be on or off by a scanning signal. When the TFT 963 is turned on, the gray level signal voltage of a picture data signal is applied to the pixel electrode 964. The potential difference between the pixel electrodes 964 and the electrode 967 of the opposite substrate causes the transmittance of the liquid crystal to be changed. This potential difference is retained for a preset time by a capacitance 965 and an auxiliary capacitance 966, even after the TFT 963 has been turned off, thereby displaying a picture.
On the semiconductor substrate, larger numbers of data lines 962 for transmitting a plurality of level voltages (gray level signal voltages) to be applied to the pixel electrodes 964 and larger numbers of the scanning lines 961 for transmitting scanning signals are arrayed in a lattice. With the aforementioned color SXGA panel, there are provided 1280×3 data lines and 1024 scanning lines. The scanning lines 961 and the data lines 962 represent marked capacitive loads because of capacitances generated at the intersections and capacitance of the liquid crystal sandwiched in-between the two substrates.
It is observed that the scanning signal is supplied by a gate driver 970 to the scanning lines 961, while the gray level signal voltage is supplied to each pixel electrode 964 by a data driver 980 via the data lines 962. The gate driver 970 and the date driver 980 are controlled by a display controller 950, which display controller 950 delivers a clock CLK or a control signal as necessary. Picture data are delivered to the data driver 980. At the present time, digital data represent mainstream picture data. Power supply voltages are supplied to the gate driver 970 and the date driver 980 from a power circuit 940.
Picture data for a complete picture image is rewritten within one frame period or usually within 1/60 second. For reproducing moving pictures, the frame period may sometimes be 1/120 sec. The picture data is sequentially selected by each scanning line every pixel row or every horizontal line. The gray level signal voltage is supplied from each data line during the time of the selection.
Meanwhile, it is sufficient for the gate driver 970 to supply a scanning signal with at least two values. On the other hand, the data driver 980 has to drive the data lines with a gray level signal voltage of multiple levels corresponding to the number of gray levels. Thus, the data driver 980 is provided with a digital-to-analog converter circuit including a digital-to-analog converter (DAC) that converts picture data into gray level signal voltages and an amplifier circuit that amplifies the gray level voltages to output the so amplified gray level voltages at the data lines 962.
In recent liquid crystal displays, a higher picture quality with more and more colors has become a preference, such that there is raised a demand for at least 260,000 colors (for picture data with 6 bits each of R, G and B) and even 26,800,000 colors (for picture data with 8 bits each of R, G and B). Hence, with a data driver that outputs the gray level signal voltages to cope with multi-bit picture data, the DAC circuit size increases with resulting increase in the chip size of the data driver LSI, thus raising the cost. To keep pace with increase in the size of a viewing area of the liquid crystal display, higher resolution is also needed to further increase the load capacitance on the data lines 962, while the one-data selection time interval (one data outputting time interval) roughly corresponding to the one frame time interval divided by the number of the gate lines is becoming shorter. For this reason, it is up to the amplifier circuit, operating as an output buffer of the driver LSI, to drive a larger load at a high speed at high voltage accuracy during a shorter one-data selection time.
As an area-saving DAC that converts the multi-bit digital data to an analog voltage signal, there is known a serial DAC that sequentially samples a reference voltage in response to time-serially input digital data and repeats charge re-distribution between the capacitances to get a level voltage.
FIG. 16 depicts a schematic circuit diagram showing an example configuration of a digital-to-analog converter circuit provided with a serial DAC disclosed in Patent Document 1 as indicated hereinbelow.
The digital-to-analog converter circuit, shown in FIG. 16, includes voltage delivery nodes N5 and N6 to which are delivered reference voltages V5 and V6, respectively. The digital-to-analog converter circuit also includes a serial DAC provided with capacitance elements C91 and C92, a changeover switch 911, and switches 912 and 913, and a voltage follower circuit 919. The capacitance element C91 has a first terminal connected to the voltage delivery node N5, while having a second terminal connected to a node N51. The capacitance element C92 has a first terminal connected to the voltage delivery node N5, while having a second terminal connected to a node N52. The changeover switch 911 connects the node N51 to the voltage delivery node N5 or N6. The switch 912 is connected between the nodes N51 and N52, while the switch 913 is connected between the node N52 and the voltage delivery node N5. The voltage follower circuit 919 is made up of a differential amplifier having a non-inverting input end (+) connected to the node N52 and having an inverting input end (−) connected to an output terminal. The capacitance elements C91 and C92 are ordinarily set to equal capacitance values.
The operation of the serial DAC, shown in FIG. 16, is now described. Initially, the switch 913 is turned on for a moment to reset the potential difference (terminal-to-terminal voltage) across both ends (N5 and N52) of the capacitance element C92 to zero.
The reference voltage V5 or V6 is sampled at the node N51, by the changeover switch 911, in response to the value of the lowermost bit data B1 out of time-serially input digital data B1 to Bk. The switch 911 is then turned off, that is, opened. The switch 912 is turned on so that electric charge is re-distributed between the capacitance elements C91 and C92. The switch 912 is then turned off so that the electric charge are retained by the capacitance element C92.
Then, responsive to the next bit data B2, the reference voltage V5 or V6 is sampled by the node N51 by the switch 911. After re-distribution of the electric charge between the capacitance elements C91, C92 by the switch 912, the electric charge, thus re-distributed, are retained by the capacitance element C92.
By the similar sequence of operations, the sample and hold operations are reiterated in the direction from the low order bit data towards the high order bit data.
In the case of K-bit data, one cycle of sample and hold operations is repeated K times. After the end of the one cycle of the sample and hold operations, the voltage at the node N52 is represented by the following equation (1):VN52=(2−1×BK+2−2×BK−1+ . . . +2−K×B1)×(V6−V5)+V5  (1)where BK, BK−1, . . . , B1 are 0 or 1.
A voltage VN52 is amplified and output as an output voltage Vout by the voltage follower circuit 919. In this manner, the digital-to-analog converter circuit is able to output 2K voltage levels corresponding to 2K equal interval divisions of the voltage range between the reference voltages V5 and V6 in response to K-bit data.
With the digital-to-analog converter circuit, shown in FIG. 16, the number of devices is not dependent on the number of data bits, with the result that the circuit size may be significantly reduced even if the number of bits is increased, thus leading to saving in the circuit area.
With the digital-to-analog converter circuit of FIG. 16, the output voltage is a linear output resulting from division by equal intervals of each voltage range between respective voltage levels. However, with the digital-to-analog converter circuit which receives input digital data of large number of bits, it is possible to select and output gray scale voltages that are in keeping with non-linear gamma characteristic of the liquid crystal.
[Patent Document 1] JP Patent Kokai Publication No. JP-A-59-154820 (FIG. 1)